A 32-bit RISC-V CPU core verified using UVM-SystemC and supports a multiplication accelerator with CDC.

Repository link

It supports

  • the RV32I Base Integer Instruction Set
  • the “Zicntr” extension
  • the “Zmmul” extension, via an accelerator running in a faster clock domain
  • some of the “Zicsr” extension, including cycle, time and instret
  • some of the privileged instruction set, like timer interrupts and exceptions

The design is written in SystemVerilog. Design verification is done using UVM-SystemC, with Verilator as the simulator, CRAVE as the constrained randomization environment, and FC4SC as the functional coverage collector.

Technical specification

Design verification document

Applications have been successfully run on a softcore CPU in an FPGA and in a verilator simulation with an emulated UART interface. They include

  • CoreMark
  • a simple FreeRTOS program

CoreMark Performance

  • Setup: RV32IM + fast multiplier clock
  • Simulated with verilator and run on an FPGA
  • 10 MHz clock
  • multiplier with a 50 MHz clock
  • On-chip RAM of 32 KB 
    2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 11482667
Total time (secs): 11
Iterations/Sec   : 18
Iterations       : 200
Compiler version : GCC15.0.0 20241225 (experimental)
Compiler flags   : -DPERFORMANCE_RUN=1 -DITERATIONS=200 -O2
Memory location  : STACK
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0x382f
Correct operation validated. See README.md for run and reporting rules.